The Effect of Clock Jitter on the Performance of Bandpass Σ∆ ADCs

In this paper, we build a novel well-proved model for describing the combined error due to clock jitter and quantization noise on the performance of bandpass sigma delta (Σ∆) analog to digital converters (ADCs). The clock jitter is modeled as a timing variation of the sampling process which follows the characteristic of the Wiener process. Computer simulations as well as theoretical calculations are performed and the two confirm each other. Results show that clock jitter severely degrades the system’s performance in terms of achievable signal to noise ratio (SNR). It is also shown that, when the clock jitter becomes more dominant compared to the quantization noise, increasing the oversampling ratio (OSR) and/or the order of Σ∆ ADCs do not improve the performance significantly. Index Terms Sigma-delta modulators, analog-to-digital conversion, clock jitter, signal-to-noise ratio.